Every technical specification, qualification parameter, and corporate claim published by Cosine Nanoelectronics is backed by verifiable documentation. Below is our public evidentiary manifest.
| Source ID | Claim Category | Audited Factual Statement | Verification Authority | Action / Link |
|---|---|---|---|---|
| SRC-01 | Corporate Registration | Cosine Nanoelectronics (Fujian) Co., Ltd. founded Nov 9, 2017 (USCC: 91350582MA318K6Y1M). | National Credit System (GSXT) | Verify Registry ↗ |
| SRC-02 | Scientific Leadership | Founded by Dr. Lizhong Sun (Fudan University PhD, National University of Singapore Postdoctoral Fellow). | CNIPA Patent Gazette | View Bio ↗ |
| SRC-03 | COS13487 RS-485 | 500 kbps, 1/8 Unit Load (256 nodes), ±15kV ESD bus protection, hardware auto-direction control. | TIA/EIA-485 Characterization | Download PDF ↗ |
| SRC-04 | COS8552 Zero-Drift | Input offset voltage Vos ≤ 5µV max at 25°C, 0.005 µV/°C drift, 1.5MHz GBW in SOP-8/MSOP-8. | Precision Analog Lab Characterization | Download PDF ↗ |
| SRC-05 | COS7202 40V LDO | 3.5V to 40V Vin range, 200mA output current, 2.5µA standby quiescent current in SOT-23-5. | Power Semiconductor Test Lab | Download PDF ↗ |
| SRC-06 | COS4427 Gate Driver | Dual 1.5A peak sink/source current, 25ns rise time at 1000pF load, 4.5V-18V operating range. | MOSFET Driver Bench Test Report | Download PDF ↗ |
| SRC-07 | Quality Management | ISO 9001-aligned Quality Management System Statement (Supplier Declaration of Conformity). | ISO 9001 Quality Assurance | Download PDF ↗ |
| SRC-08 | Environmental (RoHS 2.0) | 100% lead-free, halogen-free compliance with EU Directive 2011/65/EU and (EU) 2015/863. | European Commission (RoHS) | Download PDF ↗ |
| SRC-09 | Chemical Safety (REACH) | Candidate List Substances of Very High Concern (SVHC) do not exceed 0.1% w/w. | ECHA REACH SVHC | Download PDF ↗ |
| SRC-10 | PCN Policy | Enforcing J-STD-046 compliant 90-day PCN notices, recording 0 critical silicon changes in 2024. | JEDEC J-STD-046 | Download PDF ↗ |
| SRC-11 | Package Drawing | SOP-8 standard outline dimensions, lead-frame pin pitch, and land pattern recommendations. | JEDEC MS-012 | Download PDF ↗ |
| SRC-12 | Application Notes | Noise filtering, auto-direction bus termination calculations, and ESD transient suppression. | IEC 61000-4-2 Testing | Download PDF ↗ |
Every specification is verified using Automated Test Equipment (ATE) across wafer-level and final packaged silicon, calibrated against JEDEC, IEC, and TIA standards.
Yes. Enterprise customers and tier-1 OEMs may contact our QA department at sales@cosinechips.com to request full third-party test reports from accredited laboratories.
